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SOC ASIC CAD manager/staff/senior

发布时间:2014-07-28 发布者:-上海怡瑞投资管理咨询有限公司
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月薪:5000元~6000元

工作地点:上海市

学历:本科

工作性质:全职

经验:不限

招聘人数:3人

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职位描述

岗位职责:

受某美国公司委托,为其寻找 ASIC CAD Manager/Senior Engineer,其职位描述如下: Senior ASIC CAD Engineer - Timing Analysis Flow Job Description: - Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with company global teams. - Participate in the research of Design Methodology to improve automation and productivity to produce company's new high-quality cutting-edge products - Technical support and programming - Interface with EDA venders on technology Requirement: - Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences - Extensive Primetime experience is a must - Good working knowledge of script languages (Perl/Python/TCL) and unix shell is a must, C programming experience is also OK - Good analytic skills and problem solving skills - Good communication skills is a must. - Proficiency in English (speaking and writing) is very important in order to communicate with the team in US and other design team world-wide. Very nice to have: - design experience or Synthesis experience with DC/RC - Work experience in developing (CAD) software. - Experience working with teams in multi international sites. =================== Senior ASIC CAD Engineer – FCFP/TDFP Job Description: - Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with company global teams. - Participate in the research of Design Methodology to improve automation and productivity to produce company's new high-quality cutting-edge products - Technical support and programming - Interface with EDA venders on technology Requirement: - major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences - Good understanding of modern large chip design flow: Construction and verification. - Experience with floorplanning and/or P&R tools (Synopsys ICC, Cadence First Encounter) - Work experience with PD design or with support of PD design team. - Good working knowledge of script languages (Perl/Python/TCL)and unix shell is a must, C programming experience is also OK - Good analytic skills and problem solving skills - Good communication skills is a must. - Proficiency in English (Speaking and writing) is very important in order to communicate with the team in US and other design team world-wide. - Fast learner. Very nice to have: - Experience with Cadence First Encounter (also called EDI) for floorplanning - Work experience in developing (CAD) software. - Experience working with teams in multi international sites. - Experience with OA data base.

岗位要求:

学历要求: 本科

性别要求: 不限

年龄要求: 18周岁以上

工作年限: 不限

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