JOB DESCRIPTION - Support timing characterization flow for stand cell, io, memory, analog ip. - Support EDA design flow. - Perl/SKill/TCL script support. QUALIFICATION: - BSEE with minimum 3-year or MSEE with minimum 1-year of experience. - Stand cell library build and support with minium 1-year of experience. - Familiar with EDA design flow for mixed-signal design. - Familiar with Computer languages such as C, C++, perl/TCL/C-shell. - Familiar with IT is a plus