? Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams. ? Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing products ? Technical support and programming ? Interface with EDA venders on technology Requirements: ? Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences ? Good programming skill with one or more languages (e.g. tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow ? Experience in ASIC design (digital design, Front-end and/or Back-end) ? Familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power, place & route) and usage of related EDA tools ? Good written and spoken English ? Good communication skills and be able to work both independently and in a team Highlight: The key requirement is experience with UPF : ? UPF2.0 preferred but UPF1.0 is acceptable ? DC-T power aware synthesis ? MVRC checking on RTL used for synthesis and especially on netlist after synthesis ? Formality – both power aware with UPF and non-power aware Hands on DFT implementation experience: ? DFT scan implementation using Mentor Testkompress (short term need) or Synopsys DFTMAx (long tern need) o Understanding of scan compression logic generation and stitching of this logic into the design o Understanding of Isolation wrappers for scan