Description: 1. Be responsible for IC design flow developing, enhancing and supporting, including verification flow, IP DK (design kit) generation flow, physical design flow etc.; 2. Work with EDA vendor to develop and integrate new features in the overall design or verification flow; 3. Explore and support new flows and methodology to improve the design efficient; 4. Participate in project definition, feasibility R&D for special design cases; 5. Train and guide fresh users for new design flow release; Qualifications: 1. BS/MS in EE or relevant field in Physical Design, CAD P&R flows; 2. 8+ years of industrial experience of: ASIC, Place & Route, Physical Design, Flows Development, Floorplanning, low power design etc.; 3. Have Delivered several sub-micron ASIC tapeouts. Have Experience in closing and supporting a physical design (timing, noise, EM/IR); 4. Skilled in ICC, Encounter, Design Compiler, CeltIC, Prime Time/SI, StarRC, Virtuoso, Perl, TCL/TK, makefile, Strong Scripter; 5. Experience with design for test flows is preferred; 6. Prior experience in CPU/GPU physical design is preferred; 7. Knowledge in Synopsys tools is preferred; 8. Skilled in Makefiles is preferred.