Requirements: 1. BS or MS degree in EE or CS related 2. Experience in 65nm/55nm and below technology 3. Familiar with DFT related flow and EDA tools 4. Experienced in chip design flow and chip implementation flow is a plus 5. Proficient in Tcl and UNIX shell 6. Team work and Proactive attitudeResponsible for the development and implementation for advanced at speed testing and other DFT, JTAG, memory bist, scan chain and ATPG, for ASIC projects.